1. Technical Field
The present invention disclosed herein relates to a chip scale package and a method for manufacturing the same, and more particularly, to a wafer level chip scale package (WL-CSP), and a method for manufacturing the same, capable of enhancing the reliability of joints between solder balls and ball pads that are formed by redistribution of chip pads.
2. Description of the Related Art
Recently, the electronics industry has been focusing on manufacturing products having light weight, small size, high speed, multi-functions, high performance, and high reliability at a low cost. One of the important techniques that make it possible to attain the goal of this product design is a package assembly technique. A chip scale package (or a chip size package) is a new type of package that has recently been developed, and has many advantages compared to a typical plastic package. The biggest advantage of the chip scale package is the package size. The international semiconductor associations, such as Joint Electron Device Engineering Council (JEDEC) and Electronic Industry Association of Japan (EIAJ), define the chip scale package as having a package size no greater than 1.2 times a chip size.
The chip scale package is mainly used in products, such as digital camcorders, mobile phones, laptop computers, and memory cards, for which miniaturization and mobility are required. Semiconductor devices, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a micro-controller, etc., are mounted in the chip scale package. Further, the use of the chip scale package having a memory device, such as a dynamic random access memory (DRAM) or a flash memory, is gradually spreading. Currently, at least 50 types of chip scale packages are developed or produced all over the world.
In general, when a semiconductor wafer is produced through a wafer manufacturing process, individual chips are separated from the wafer and undergo a package assembly process. The package assembly process is separate from the wafer production process because the equipment and raw and subsidiary materials for the package assembly process are different from those for the wafer manufacturing process. However, when chip scale packages are manufactured at the wafer level, the package is produced as a complete product without separating the individual chips from the wafer. As such, the existing equipment and processes for manufacturing the wafer can also be used for producing the package. This means that the raw and subsidiary materials, which are additionally necessary to produce the chip scale package, can be reduced.
FIG. 1 is a plan view of a chip scale package according to the conventional art. FIG. 2 is a cross-sectional view of the chip scale package of FIG. 1 taken along the line I-I. Referring to FIGS. 1 and 2, the chip scale package 20 includes a substrate 14, which may be a portion of a semiconductor wafer 12. Chip pads 11 are formed on the substrate 14. A passivation layer 22 is formed on the substrate 14 and the chip pads 11 such that portions of the chip pads 11 are exposed through the passivation layer 22. A first dielectric layer 25 is formed on the passivation layer 22 and defines openings exposing the chip pads 11. Metal trace layer patterns 21 are disposed on the first dielectric layer 25 and electrically connect the chip pads 11 to the solder balls 28. The metal trace layer patterns 21 include ball pad sections 23 where the solder balls 28 are placed. A second dielectric layer 24 is formed on the metal trace layer patterns 21 and the first dielectric layer 25. The second dielectric layer 24 defines openings 27 that expose the ball pad sections 23.
According to the conventional method, as illustrated in FIGS. 1 and 2, the contact surface area between the solder balls 28 and the ball pad sections 23 is limited to the flat surface area of the ball pad sections 23. Thus, the reliability of the joints between the solder balls 28 and the ball pad sections 23 is fixed. Further, since the ball pad sections 23 are circular metal plates, undesirable parasitic capacitance associated with the ball pad sections 23 is maximized. The present invention addresses these and other disadvantages of the conventional art.